I. Field of the Disclosure
The technology of the disclosure relates generally to memory structures in computing devices.
II. Background
Memory for computing devices comes in a variety of forms. Random Access Memory (RAM) is commonly used by operating systems and applications within computing devices, and is provided in two different types. Static RAM (SRAM) holds its charge indefinitely without a need for external power. In contrast, dynamic RAM (DRAM) stores each bit of data in a capacitor, which leaks charge over time and must periodically be refreshed.
Recent proposals in the DRAM standard have indicated a desire to have additional information flow back from the DRAM to an applications processor (AP) or a System on a Chip (SoC). Historically, such information is provided across a physical layer (PHY) of the DRAM, and only a data plane (DQ) is bidirectional. In the next generation of Low Power DRAM (LP-DRAM), the proposals add error detection or correction information and specifically add cyclic redundancy checking (CRC) information to the information that is passed back to the SoC. While adding CRC information has been effectuated in the double data rate (DDR) release 4 (DDR4), it has not been done in the low power (LP) DDR5 DRAM environment. Adding CRC to the LP DDR5 standard will allow missed transmissions to be re-transmitted, avoiding catastrophic system failure.
An additional change that has been requested by some of the DRAM vendors is greater control over the refresh rate. The need for greater control over the refresh rate arises from the increasingly weak charge that is held in modern DRAM capacitors. Under the old rules, the charges were refreshed periodically based on the weakest DRAM.
Thus, there is a need to allow for CRC communication and there needs to be a way for the DRAM to indicate to the SoC that a particular type of refresh (e.g., bank, row, full refresh) is needed by the DRAM.